Electrostatic discharge (ESD) is a phenomenon known to degrade or destroy electronic components. In particular, given the decreasing size of circuit features with ever improving process technology, static electricity can destroy or substantially harm many of today's integrated circuits. Electrostatic discharge can occur, for example, from human handling, automated circuit testing or as a packaged circuit slides on its pins across another surface. The circuits most susceptible to damage are unpackaged or packaged finished circuits which have not yet been installed into a finished product. Once installed, for example, onto a circuit card, other means exist to protect the circuits from damage.
Various techniques have been employed to protect integrated circuit chips handled by humans during the fabrication process. These methods include special handling procedures, use of grounding equipment, and the addition of protective components to the chip circuitry. The most popular technique used to protect complementary metal-oxide semiconductor (CMOS) circuits from ESD is the addition of diffused or implanted dual clamping diodes to clamp input and/or output voltages to within the boundaries of the chip's power supply connections. Such dual diodes are coupled between the input paths of the circuit and the pins to which the power supplies are connected. With an electrostatic discharge event of one polarity, a first diode is forward-biased and with a discharge of the opposite polarity, the second diode is forward-biased. Other methods used for protecting CMOS circuits from electrostatic discharge damage are almost always variations on this dual diode clamping approach.
The ESD dissipation methods described above typically function satisfactorily for integrated circuits with large features. However, as the features of integrated circuits approach one micron and smaller, lower voltages than those which damage the larger feature circuits can destroy these more sensitive circuits. Many integrated circuit cards today comprise hybrid cards wherein the normal signal voltages of a chip must often be allowed to exceed normal power supply voltage levels. This is commonly the situation where a CMOS chip powered at 3.3 volts shares an interface bus with older technology integrated circuit chips powered at 5 volts. In such a case, the conventional dual diode protection method described above is unworkable since in operation the power supply connections would restrict voltage on the input and/or output nodes of the CMOS chip.
Thus, there exists a need in the integrated circuit art for a novel ESD suppression circuit for protecting packaged and unpackaged integrated circuit chips which acknowledges the integrated circuit chips' full functionality in subsequently established multi-level power supply environments.